1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of Related Art
As the function of a microprocessor becomes more powerful, the program and calculation of software becomes more complicate, and thus the need for Dynamic Random Access Memory (DRAM) storage memory is increased. As the number of semiconductor devices incorporated in an integrated circuit increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is widely used. In FIG. 1. a circuit diagram of a DRAM memory cell is shown. A capacitor C is used to store information as binary data by charging/discharging states. Normally, a binary bit is stored in each capacitor. When the capacitor C is free of charge, logic "0" is presented, whereas when the capacitor is fully charged, logic "1" is presented. In general, a dielectric film 101 is deposited between a top electrode (cell electrode) 102 and a bottom electrode (storage electrode) 100. The capacitor C is electrically coupled with a bit line BL. The read/write operation of a DRAM memory cell is performed by the charging/discharging states of the capacitor C. The bit line BL is connected to the drain of the transfer field effect transistor T. The capacitor C is connected to the source of the transfer field effect transistor T. A signal transmitted through a gate of the transfer field effect transistor T is used to control the capacitor C to turn on or turn off the connection with the bit line BL. In other words, the transfer field effect transistor T acts as a switch to control the charging or discharging state of the capacitor C.
In the DRAM manufacturing process, a two-dimensional capacitor named a planar type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the electrode of a semiconductor substrate, and thus the electrode is required to have a large area. This type of memory cell is therefore not suitable to be used in a DRAM having a high degree of integration. For a high integration DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced.
With stack-type or trench-type capacitors, it has been made possible to obtain a larger memory without increasing the volume. However, to realize a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type, turns out to be insufficient.
One solution for improving the capacitance of a capacitor is to use the fin-type stacked capacitor. The fin-type stacked capacitor includes electrodes and dielectric layers which extend in a fin shape in a plurality of stacked layers. Hence, the surface area of the electrode is enlarged, the capacitance is increased. Refer to Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pp. 592-595, December 1988, and the U.S. Pat. Nos. 5,071,783, 5,126,810, and 5,206,787.
Another solution for improving the capacitance of a capacitor is to use the cylindrical-type stacked capacitor. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. Refer to Wakamiya et al., Novel Stacked Capacitor Cell for 64-Mb DRAM, 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70, and the U.S. Pat. No. 5,077,688.
With the trend toward high integration density, the size of the DRAM cell must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacitance. Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of .alpha.-rays is increased.